High-speed VLSI interconnections / (Record no. 41845)
[ view plain ]
| 000 -LEADER | |
|---|---|
| fixed length control field | 15360nam a2200961 i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 5201516 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | IEEE |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20191218152111.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS | |
| fixed length control field | m o d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr |n||||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 071115t20152007njua ob 001 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9780470165973 |
| Qualifying information | electronic |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 9780471780465 |
| Qualifying information | paper |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 0470165979 |
| Qualifying information | electronic |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1002/9780470165973 |
| Source of number or code | doi |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (CaBNVSL)mat05201516 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (IDAMS)0b0000648104a9c0 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | CaBNVSL |
| Language of cataloging | eng |
| Description conventions | rda |
| Transcribing agency | CaBNVSL |
| Modifying agency | CaBNVSL |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK7874.7 |
| Item number | .G63 2007eb |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.39/5 |
| Edition number | 22 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Goel, Ashok K., |
| Dates associated with a name | 1953- |
| Relator term | author. |
| 245 10 - TITLE STATEMENT | |
| Title | High-speed VLSI interconnections / |
| Statement of responsibility, etc. | Ashok K. Goel. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 2nd ed. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | Hoboken, New Jersey : |
| Name of producer, publisher, distributor, manufacturer | Wiley-Interscience, |
| Date of production, publication, distribution, manufacture, or copyright notice | c2007. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1 PDF (xix, 407 pages) : |
| Other physical details | illustrations. |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | electronic |
| Source | isbdmedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Source | rdacarrier |
| 490 1# - SERIES STATEMENT | |
| Series statement | Wiley series in microwave and optical engineering ; |
| Volume/sequential designation | 185 |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE | |
| Bibliography, etc. note | Includes bibliographical references and index. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Preface -- 1. Preliminary Concepts and More -- 1.1 Interconnections for VLSI Applications -- 1.1.1 Metallic Interconnections - Multilevel, Multilayer and Multipath Configurations -- 1.1.2 Optical Interconnections -- 1.1.3 Superconducting Interconnections -- 1.2 Copper Interconnections -- 1.2.1 Advantages of Copper Interconnections -- 1.2.2 Challenges Posed by Copper Interconnections -- 1.2.3 Fabrication Processes for Copper Interconnections -- 1.2.4 Damascene Processing of Copper Interconnections -- 1.3 Method of Images -- 1.4 Method of Moments -- 1.5 Even and Odd Mode Capacitances -- 1.5.1 Two Coupled Conductors -- 1.5.2 Three Coupled Conductors -- 1.6 Transmission Line Equations -- 1.7 Miller's Theorem -- 1.8 Inverse Laplace Transformation -- 1.9 A Resistive Interconnection as a Ladder Network -- 1.9.1 Open Circuit Interconnection -- 1.9.2 Short Circuited Interconnection -- 1.9.3 Application of the Ladder Approximation to a Multipath Interconnection -- 1.10 Propagation Modes in a Microstrip Interconnection -- 1.11 Slow-Wave Mode Propagation -- 1.11.1 Quasi-TEM Analysis -- 1.11.2 Comparison with Experimental Results -- 1.12 Propagation Delays -- Exercises -- References -- 2. Parasitic Resistances, Capacitances and Inductances -- 2.1 Parasitic Resistances - General Considerations -- 2.2 Parasitic Capacitances - General Considerations -- 2.2.1 Parallel Plate Capacitance -- 2.2.2 Fringing Capacitances -- 2.2.3 Coupling Capacitances -- 2.3 Parasitic Inductances - General Considerations -- 2.3.1 Self and Mutual Inductances -- 2.3.2 Partial Inductances -- 2.3.3 Methods for Inductance Extraction -- 2.3.4 Effect of Inductances on Interconnection Delays -- 2.4 Approximate Formulas for Capacitances -- 2.4.1 Single Line on a Ground Plane -- 2.4.2 Two Lines on a Ground Plane -- 2.4.3 Three Lines on a Ground Plane -- 2.4.4 Single Plate with Finite Dimensions on a Ground Plane -- 2.5 The Green's Function Method - Using Method of Images. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 2.5.1 Green's Function Matrix for Interconnections Printed on the Substrate -- 2.5.2 Green's Function Matrix for Interconnections Embedded in the Substrate -- 2.5.3 Application of the Method of Moments -- 2.5.4 Even and Odd Mode Capacitances -- 2.5.5 Ground and Coupling Capacitances -- 2.5.6 The Program IPCSGV -- 2.5.7 Parametric Dependence of Interconnection Capacitances -- 2.6 The Green's Function Method - Fourier Integral Approach -- 2.6.1 Green's Function for Multilevel Interconnections -- 2.6.2 Multiconductor Interconnection Capacitances -- 2.6.3 Piecewise Linear Charge Distribution Function -- 2.6.4 Calculation of Interconnection Capacitances -- 2.7 The Network Analogue Method -- 2.7.1 Representation of Subregions by Network Analogues -- 2.7.2 Diagonalized System for Single Level Interconnections -- 2.7.3 Diagonalized System for Multilevel Interconnections -- 2.7.4 Interconnection Capacitances and Inductances -- 2.7.5 The Program "ICIMPGV" -- 2.7.6 Parametric Dependence of Interconnection Capacitances -- 2.7.7 Parametric Dependence of Interconnection Inductances -- 2.8 Simplified Formulas for Interconnection Capacitances and Inductances on Silicon and GaAs Substrates -- 2.8.1 Line Capacitances and Inductances -- 2.8.2 Coupling Capacitances and Inductances -- 2.9 Inductance Extraction Using FastHenry -- 2.9.1 The Program "FastHenry" -- 2.9.2 Extraction Results Using FastHenry -- 2.10 Copper Interconnections - Resistance Modeling -- 2.10.1 Effect of Surface/Interface Scattering on the Interconnection Resistivity -- 2.10.2 Effect of Diffusion Barrier on the Interconnection Resistivity -- 2.11 Electrode Capacitances in a GaAs MESFET - An Application of the Program IPCSGV -- 2.11.1 Ground and Coupling Capacitances -- 2.11.2 The Program "EPCSGM" -- 2.11.3 Dependence on MESFET Dimensions -- 2.11.4 Comparison with Internal MESFET Capacitances -- Exercises -- References -- 3. Interconnection Delays -- 3.1 Metal-Insulator-Semiconductor Microstrip Line Model of an Interconnection. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 3.1.1 The Model -- 3.1.2 Simulation Results -- 3.2 Transmission Line Analysis of Single Level Interconnections -- 3.2.1 The Model -- 3.2.2 The Program "PDSIGV" -- 3.2.3 Dependence on Interconnection Parameters -- 3.3 Transmission Line Analysis of Parallel Multilevel Interconnections -- 3.3.1 The Model -- 3.3.2 Numerical Simulation Results -- 3.4 Analysis of Crossing Interconnections -- 3.4.1 Simplified Analysis of Crossing Interconnections -- 3.4.2 Comprehensive Analysis of Crossing Interconnections -- 3.4.3 The Program "SPBIGV" -- 3.4.4 Simulation Results Using SPBIGV3.5Parallel Interconnections Modeled as Multiple Coupled Microstrips -- 3.5.1 The Model -- 3.5.2 Simulation Results -- 3.6 Modeling of Lossy Parallel and Crossing Interconnections as Coupled Lumped Distributed Systems -- 3.6.1 The Model -- 3.6.2 Simulation Results -- 3.7 Very High Frequency Losses in a Microstrip Interconnection -- 3.7.1 The Model -- 3.7.2 Simulation Results -- 3.7.3 Interconnection Delays With the High-Frequency Effects -- 3.8 Compact Expressions for Interconnection Delays -- 3.8.1 The RC Interconnection Model -- 3.8.2 The RLC Interconnection Model - A Single Semi-Infinite Line -- 3.8.3 The RLC Interconnection Model - A Single Finite Line -- 3.8.4 Single RLC Interconnection - Delay Time -- 3.8.5 Two and Three Coupled RLC Interconnections - Delay Times -- 3.9 Interconnection Delays in Multilayer Integrated Circuits -- 3.9.1 The Simplified Model -- 3.9.2 Simulation Results and Discussion -- 3.10 Active Interconnections -- 3.10.1 Interconnection Delay Model -- 3.10.2 Active Interconnection Driven by Minimum Size Inverters -- 3.10.3 Active Interconnection Driven by Optimum Size Inverters -- 3.10.4 Active Interconnection Driven by Cascaded Inverters -- 3.10.5 Dependence of Propagation Time on the Interconnection Driving Mechanism -- Exercises -- References -- 4. Crosstalk Analysis -- 4.1Lumped Capacitance Approximation -- 4.2Coupled Multiconductor MIS Microstrip Line Model of Single Level Interconnections. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 4.2.1 The Model -- 4.2.2 Numerical Simulations -- 4.2.3 Crosstalk Reduction -- 4.3 Frequency Domain Modal Analysis of Single Level Interconnections -- 4.3.1 The General Technique -- 4.3.2 Two-Line System -- 4.3.3 Three-Line System -- 4.3.4 Four-Line System -- 4.3.5 Simulation Results -- 4.4 Transmission Line Analysis of Parallel Multilevel Interconnections -- 4.4.1 The Model -- 4.4.2 The Program "DCMPVI" -- 4.4.3 Numerical Simulations Using DCMPVI -- 4.5 Analysis of Crossing Interconnections -- 4.5.1 Effect of Crossing Interconnections -- 4.5.2 Comprehensive Analysis of Crossing Interconnections -- 4.6 Compact Expressions for Crosstalk Analysis -- 4.6.1 Distributed RC Model for Two Coupled Interconnections -- 4.6.2 Distributed RLC Model for Two Coupled Interconnections -- 4.6.3 Distributed RLC Model for Three Coupled Interconnections -- 4.7 Multiconductor Buses in GaAs High-Speed Logic Circuits -- 4.7.1 The Model -- 4.7.2 Lossless MBUS with Cyclic Boundary Conditions -- 4.7.3 Simulation Results -- Exercises -- References -- 5. Electromigration-Induced Failure Analysis -- 5.1 Electromigration in VLSI Interconnection Metallizations - An Overview -- 5.1.1 Problems Caused by Electromigration -- 5.1.2 Electromigration Mechanism and Factors -- 5.1.3 Electromigration Under Pulsed-DC and AC Conditions -- 5.1.4 Testing and Monitoring of Electromigration -- 5.1.5 General Guidelines for Testing Electromigration -- 5.1.6 Reduction of Electromigration -- 5.2 Models of IC Reliability -- 5.2.1 Arrhenius Model -- 5.2.2 Mil-Hdbk-217D Model -- 5.2.3 Series Model -- 5.2.4 Series-Parallel Model -- 5.3 Modeling of Electromigration Due to Repetitive Pulsed Currents -- 5.3.1 Modeling of Physical Processes -- 5.3.2 First-Order Model Development -- 5.3.3 Modeling Results for DC Currents -- 5.3.4 Modeling Results for Pulsed Currents -- 5.4 Electromigration in the Copper Interconnections -- 5.4.1 Electromigration Under DC Conditions -- 5.4.2 Electromigration Under Pulsed DC Condition. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 5.4.3 Electromigration Under Bipolar AC Conditions -- 5.5 Failure Analysis of VLSI Interconnection Components -- 5.5.1 Reduction of Components into Straight Segments -- 5.5.2 Calculation of MTF and Lognormal Standard Deviation -- 5.5.3 The Program "EMVIC" -- 5.5.4 Simulation Results Using EMVIC -- 5.6 Computer-Aided Failure Analysis -- 5.6.1 "RELIANT" for Reliability of VLSI Interconnections -- 5.6.2 "SPIDER" for Checking Current Density and Voltage Drops in the Interconnection Metallizations -- Exercises -- References -- 6. Future Interconnections -- 6.1 Optical Interconnections -- 6.1.1 Advantages of Optical Interconnections -- 6.1.2 Systems Issues and Challenges -- 6.1.3 Material Processing Issues and Challenges -- 6.1.4 Design Issues and Challenges -- 6.2 Transmission Line Models of Lossy Waveguide Interconnections -- 6.2.1 Lossy Waveguide with Single Propagating Wave -- 6.2.2 Equivalent Circuits for Waveguide Drivers and Loads -- 6.2.3 Lossy Waveguide in an Inhomogenous Medium -- 6.3 Superconducting Interconnections -- 6.3.1 Advantages of Superconducting Interconnections -- 6.3.2 Propagation Characteristics of Superconducting Interconnections -- 6.3.3 Comparison with Normal Metal Interconnections -- 6.4 Nanotechnology Circuit Interconnections - Potential Technologies -- 6.4.1 Silicon Nanowires and Metallic Interconnections -- 6.4.2 Nanotube Interconnections -- 6.4.3 Quantum Cell Based Wireless Interconnections -- 6.5 Nanotube Integrated Circuits -- 6.5.1 Nanotube Interconnections and Vias -- 6.5.2 Comparison of Nanotube and Copper Interconnections -- 6.5.3 Nanotubes for High Frequency Applications -- Exercises -- References -- CD-ROM -- Appendix 2.1: Listing of the Program "IPCSGV" for Calculating the Parasitic Capacitances for Single Level Interconnections on GaAs-Based VLSI Using the Green's Function Method -- Appendix 2.2: Listing of the Program "ICIMPGV" for Calculating the Parasitic Capacitances and Inductances for Multilevel Interconnections on GaAs-Based VLSI Using the Network Analogue Method. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Appendix 2.3: Listing of the Program "EPCSGM" for Calculating the Electrode Parasitic Capacitances in a Single-Gate GaAs MESFET -- Appendix 3.1: Listing of the Program "PDSIGV" for Calculating the Propagation Delays in the Single Level Interconnections on GaAs-Based VLSI -- Appendix 3.2: Listing of the Program "IPDMSR" for Calculating the Propagation delays in an Interconnection Driven by Minimum Size Repeaters -- Appendix 3.3: Listing of the Program "IPDOSR" for Calculating the Propagation delays in an Interconnection Driven by Optimum Size Repeaters -- Appendix 3.4: Listing of the Program "IPDCR" for Calculating the Propagation delays in an Interconnection Driven by Cascaded Repeaters -- Appendix 4.1: Listing of the Program "DCMPVI" for Delay and Crosstalk Analysis of Multilevel Parallel VLSI Interconnections -- Appendix 4.2: Listing of the Program "SPBIGV" for Signal Propagation Analysis of Bilevel Crossing Interconnections on GaAs-Based VLSI -- Appendix 5.1: Listing of the Program "EMVIC" for Electromigration-Induced Failure Analysis of VLSI Interconnection Components -- Index. |
| 506 1# - RESTRICTIONS ON ACCESS NOTE | |
| Terms governing access | Restricted to subscribers or individual electronic text purchasers. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | This Second Edition focuses on emerging topics and advances in the field of VLSI interconnections In the decade since High-Speed VLSI Interconnections was first published, several major developments have taken place in the field. Now, updated to reflect these advancements, this Second Edition includes new information on copper interconnections, nanotechnology circuit interconnects, electromigration in the copper interconnections, parasitic inductances, and RLC models for comprehensive analysis of interconnection delays and crosstalk. Each chapter is designed to exist independently or as a part of one coherent unit, and several appropriate exercises are provided at the end of each chapter, challenging the reader to gain further insight into the contents being discussed. Chapter subjects include: * Preliminary Concepts * Parasitic Resistances, Capacitances, and Inductances * Interconnection Delays * Crosstalk Analysis * Electromigration-Induced Failure Analysis * Future Interconnections High-Speed VLSI Interconnections, Second Edition is an indispensable reference for high-speed VLSI designers, RF circuit designers, and advanced students of electrical engineering. |
| 530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE | |
| Additional physical form available note | Also available in print. |
| 538 ## - SYSTEM DETAILS NOTE | |
| System details note | Mode of access: World Wide Web. |
| 588 ## - SOURCE OF DESCRIPTION NOTE | |
| Source of description note | Description based on PDF viewed 12/19/2015. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Very high speed integrated circuits |
| General subdivision | Mathematical models. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Very high speed integrated circuits |
| General subdivision | Defects |
| -- | Mathematical models. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Integrated circuits |
| General subdivision | Very large scale integration |
| -- | Computer simulation. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Semiconductors |
| General subdivision | Junctions. |
| 655 #0 - INDEX TERM--GENRE/FORM | |
| Genre/form data or focus term | Electronic books. |
| 695 ## - | |
| -- | Advertising |
| 695 ## - | |
| -- | Aluminum |
| 695 ## - | |
| -- | Analytical models |
| 695 ## - | |
| -- | Books |
| 695 ## - | |
| -- | Boundary conditions |
| 695 ## - | |
| -- | Capacitance |
| 695 ## - | |
| -- | Computational modeling |
| 695 ## - | |
| -- | Conductors |
| 695 ## - | |
| -- | Copper |
| 695 ## - | |
| -- | Crosstalk |
| 695 ## - | |
| -- | Current density |
| 695 ## - | |
| -- | Delay |
| 695 ## - | |
| -- | Electromigration |
| 695 ## - | |
| -- | Force |
| 695 ## - | |
| -- | Indexes |
| 695 ## - | |
| -- | Integrated circuit interconnections |
| 695 ## - | |
| -- | Integrated circuit modeling |
| 695 ## - | |
| -- | Ions |
| 695 ## - | |
| -- | Materials |
| 695 ## - | |
| -- | Metallization |
| 695 ## - | |
| -- | Metals |
| 695 ## - | |
| -- | Microstrip |
| 695 ## - | |
| -- | Optical device fabrication |
| 695 ## - | |
| -- | Optical interconnections |
| 695 ## - | |
| -- | Optical variables control |
| 695 ## - | |
| -- | Optical waveguides |
| 695 ## - | |
| -- | Power transmission lines |
| 695 ## - | |
| -- | Resistance |
| 695 ## - | |
| -- | Sections |
| 695 ## - | |
| -- | Silicon |
| 695 ## - | |
| -- | Solid modeling |
| 695 ## - | |
| -- | Very large scale integration |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | IEEE Xplore (Online service), |
| Relator term | distributor. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Print version: |
| International Standard Book Number | 9780471780465 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| Uniform title | Wiley series in microwave and optical engineering ; |
| Volume/sequential designation | 185 |
| 856 42 - ELECTRONIC LOCATION AND ACCESS | |
| Materials specified | Abstract with links to resource |
| Uniform Resource Identifier | https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5201516 |
No items available.