Semiconductor memories : (Record no. 42055)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 05329nam a2201021 i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 5264189 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | IEEE |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20191218152116.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS | |
| fixed length control field | m o d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr |n||||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 151221s2002 njua ob 001 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9780470546406 |
| Qualifying information | electronic |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 9780780310001 |
| Qualifying information | |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 0470546409 |
| Qualifying information | electronic |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1109/9780470546406 |
| Source of number or code | doi |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (CaBNVSL)mat05264189 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (IDAMS)0b000064810c409f |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | CaBNVSL |
| Language of cataloging | eng |
| Description conventions | rda |
| Transcribing agency | CaBNVSL |
| Modifying agency | CaBNVSL |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK7895.M4 |
| Item number | S49 1997eb |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.39/732 |
| Edition number | 22 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Sharma, Ashok K., |
| Relator term | author. |
| 245 10 - TITLE STATEMENT | |
| Title | Semiconductor memories : |
| Remainder of title | technology, testing, and reliability / |
| Statement of responsibility, etc. | Ashok K. Sharma. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | Piscataway, New Jersey : |
| Name of producer, publisher, distributor, manufacturer | IEEE Press, |
| Date of production, publication, distribution, manufacture, or copyright notice | c1997. |
| 264 #2 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | [Piscataqay, New Jersey] : |
| Name of producer, publisher, distributor, manufacturer | IEEE Xplore, |
| Date of production, publication, distribution, manufacture, or copyright notice | [2002] |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1 PDF (xii, 462 pages) : |
| Other physical details | illustrations. |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | electronic |
| Source | isbdmedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Source | rdacarrier |
| 500 ## - GENERAL NOTE | |
| General note | "IEEE order number: PC3491"--P. [4] cover. |
| 500 ## - GENERAL NOTE | |
| General note | "IEEE Solid-State Circuits Council, sponsor." |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE | |
| Bibliography, etc. note | Includes bibliographical references and index. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Preface -- Chapter 1: Introduction -- Chapter 2: Random Access Memory Technologies -- 2.1 Introduction -- 2.2 Static Random Access Memories (SRAMs) -- 2.3 Dynamic Random Access Memories (DRAMs) -- Chapter 3: Nonvolatile Memories -- 3.1 Introduction -- 3.2 Masked Read-Only Memories (ROMs) -- 3.3 Programmable Read-Only Memories (PROMs) -- 3.4 Erasable (UV)-Programmable Read-Only Memories (EPROMs) -- 3.5 Electrically Erasable PROMs (EEPROMs) -- 3.6 Flash Memories (EPROMs or EEPROMs) -- Chapter 4: Memory Fault Modeling and Testing -- 4.1 Introduction . . . -- 4.2 RAM Fault Modeling -- 4.3 RAM Electrical Testing -- 4.4 RAM Pseudorandom Testing -- 4.5 Megabit DRAM Testing -- 4.6 Nonvolatile Memory Modeling and Testing -- 4.7 IDDQ Fault Modeling and Testing -- 4.8 Application Specific Memory Testing -- Chapter 5: Memory Design for Testability and Fault Tolerance -- 5.1 General Design for Testability Techniques -- 5.2 RAM Built-in Self-Test (BIST) -- 5.3 Embedded Memory DFT and BIST Techniques -- 5.4 Advanced BIST and Built-in Self-Repair Architectures -- 5.5 DFT and BIST for ROMs -- 5.6 Memory Error-Detection and Correction Techniques -- 5.7 Memory Fault-Tolerance Designs -- Chapter 6: Semiconductor Memory Reliability -- 6.1 General Reliability Issues -- 6.2 RAM Failure Modes and Mechanisms -- 6.3 Nonvolatile Memory Reliability -- 6.4 Reliability Modeling and Failure Rate Prediction -- 6.5 Design for Reliability -- 6.6 Reliability Test Structures -- 6.7 Reliability Screening and Qualification -- Chapter 7: Semiconductor Memory Radiation Effects -- 7.1 Introduction -- 7.2 Radiation Effects -- 7.3 Radiation-Hardening Techniques -- 7.4 Radiation Hardness Assurance and Testing -- Chapter 8: Advanced Memory Technologies -- 8.1 Introduction -- 8.2 Ferroelectric Random Access Memories (FRAMs) -- 8.3 Gallium Arsenide (GaAs) FRAMs -- 8.4 Analog Memories -- 8.5 Magnetoresistive Random Access Memories (MRAMs) -- 8.6 Experimental Memory Devices -- Chapter 9: High-Density Memory Packaging Technologies. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 9.1 Introduction -- 9.2 Memory Hybrids and MCMs (2-D) -- 9.3 Memory Stacks and MCMs (3-D) -- 9.4 Memory MCM Testing and Reliability Issues -- 9.5 Memory Cards -- 9.6 High-Density Memory Packaging Future Directions -- Index. |
| 506 1# - RESTRICTIONS ON ACCESS NOTE | |
| Terms governing access | Restricted to subscribers or individual electronic text purchasers. |
| 530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE | |
| Additional physical form available note | Also available in print. |
| 538 ## - SYSTEM DETAILS NOTE | |
| System details note | Mode of access: World Wide Web |
| 588 ## - SOURCE OF DESCRIPTION NOTE | |
| Source of description note | Description based on PDF viewed 12/21/2015. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Semiconductor storage devices. |
| 655 #0 - INDEX TERM--GENRE/FORM | |
| Genre/form data or focus term | Electronic books. |
| 695 ## - | |
| -- | Arrays |
| 695 ## - | |
| -- | Assembly |
| 695 ## - | |
| -- | Built-in self-test |
| 695 ## - | |
| -- | CMOS integrated circuits |
| 695 ## - | |
| -- | CMOS technology |
| 695 ## - | |
| -- | Capacitors |
| 695 ## - | |
| -- | Ceramics |
| 695 ## - | |
| -- | Circuit faults |
| 695 ## - | |
| -- | Clocks |
| 695 ## - | |
| -- | Complexity theory |
| 695 ## - | |
| -- | Contamination |
| 695 ## - | |
| -- | Cosmic rays |
| 695 ## - | |
| -- | Decoding |
| 695 ## - | |
| -- | Dielectrics |
| 695 ## - | |
| -- | EPROM |
| 695 ## - | |
| -- | Earth |
| 695 ## - | |
| -- | Electron traps |
| 695 ## - | |
| -- | Electronics packaging |
| 695 ## - | |
| -- | Ferroelectric films |
| 695 ## - | |
| -- | Films |
| 695 ## - | |
| -- | Indexes |
| 695 ## - | |
| -- | Integrated circuit modeling |
| 695 ## - | |
| -- | Ions |
| 695 ## - | |
| -- | Latches |
| 695 ## - | |
| -- | Lead |
| 695 ## - | |
| -- | Logic gates |
| 695 ## - | |
| -- | MOS devices |
| 695 ## - | |
| -- | Materials |
| 695 ## - | |
| -- | Nonvolatile memory |
| 695 ## - | |
| -- | Orbits |
| 695 ## - | |
| -- | Packaging |
| 695 ## - | |
| -- | Passivation |
| 695 ## - | |
| -- | Programming |
| 695 ## - | |
| -- | Protons |
| 695 ## - | |
| -- | Random access memory |
| 695 ## - | |
| -- | Registers |
| 695 ## - | |
| -- | Reliability |
| 695 ## - | |
| -- | Satellites |
| 695 ## - | |
| -- | Shift registers |
| 695 ## - | |
| -- | Stress |
| 695 ## - | |
| -- | Substrates |
| 695 ## - | |
| -- | Testing |
| 695 ## - | |
| -- | Transistors |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | John Wiley & Sons, |
| Relator term | publisher. |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | IEEE Solid-State Circuits Council. |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | IEEE Xplore (Online service), |
| Relator term | distributor. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Print version: |
| International Standard Book Number | 9780780310001 |
| 856 42 - ELECTRONIC LOCATION AND ACCESS | |
| Materials specified | Abstract with links to resource |
| Uniform Resource Identifier | https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5264189 |
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