Frequency acquisition techniques for phase locked loop / (Record no. 42423)
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| fixed length control field | 10400nam a2201141 i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 6331041 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | IEEE |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20191218152123.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS | |
| fixed length control field | m o d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr |n||||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 151222s2012 nju ob 001 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781118383285 |
| Qualifying information | ebook |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 9781118168103 |
| Qualifying information | |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 1118383281 |
| Qualifying information | electronic |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1002/9781118383285 |
| Source of number or code | doi |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (CaBNVSL)mat06331041 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (IDAMS)0b0000648193dda6 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | CaBNVSL |
| Language of cataloging | eng |
| Description conventions | rda |
| Transcribing agency | CaBNVSL |
| Modifying agency | CaBNVSL |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK7872.P38 |
| Item number | T34 2012eb |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3815/364 |
| Edition number | 23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Talbot, Daniel |
| Fuller form of name | (Daniel B.) |
| Relator term | author. |
| 245 10 - TITLE STATEMENT | |
| Title | Frequency acquisition techniques for phase locked loop / |
| Statement of responsibility, etc. | author Daniel Talbot. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | Hoboken, New Jersey : |
| Name of producer, publisher, distributor, manufacturer | John Wiley & Sons, Inc., |
| Date of production, publication, distribution, manufacture, or copyright notice | [2012] |
| 264 #2 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | [Piscataqay, New Jersey] : |
| Name of producer, publisher, distributor, manufacturer | IEEE Xplore, |
| Date of production, publication, distribution, manufacture, or copyright notice | [2012] |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1 PDF (224 pages). |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | electronic |
| Source | isbdmedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Source | rdacarrier |
| 500 ## - GENERAL NOTE | |
| General note | In Wiley online library |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE | |
| Bibliography, etc. note | Includes bibliographical references and index. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Preface xi -- 1 Introduction 1 -- 2 A Review of PLL Fundamentals 3 -- 2.1 What is a PLL?, 3 -- 2.2 Second-Order PLL, 7 -- 2.3 Second-Order PLL Type One, 7 -- 2.4 Second-Order PLL Type Two, 7 -- 2.5 Higher-Order PLL's, 8 -- 2.6 Disturbances, 8 -- 2.7 Frequency Steering and Capture, 9 -- 2.8 Effect of DC Offsets or Noise Prior to the Loop Filter, 10 -- 2.9 Injection-Locked Oscillations, 15 -- 3 Simulating the PLL Linear Operation Mode 17 -- 3.1 Linear Model, 17 -- 3.2 A Word About Damping, 19 -- 4 Sideband Suppression Filtering 21 -- 4.1 Reference Sidebands and VCO Pushing, 21 -- 4.2 Superiority of the Cauer (or Elliptical) Filter, 22 -- 5 Pros and Cons of Sampled Data Phase Detection 25 -- 5.1 What are the Forms of Sampled Data Phase Detectors?, 25 -- 5.2 A. Ramp and Sample Analog Phase Detector, 25 -- 5.3 B. The RF Sampling Phase Detector, 28 -- 5.4 C. Edge-Triggered S-R Flip-Flop, 29 -- 5.5 D. Edge-Triggered Flip-Flop Ensemble, 31 -- 5.6 E. Sample and Hold as a Phase Detector, 31 -- 6 Phase Compression 33 -- 7 Hard Limiting of a Signal Plus Noise 35 -- 8 Phase Noise and Other Spurious Interferers 39 -- 8.1 The Mechanism for Phase Noise in an Oscillator, 42 -- 8.2 Additive Noise in an FM Channel and the Bowtie, 42 -- 8.3 Importance of FM Theory to Frequency Acquisition, 45 -- 9 Impulse Modulation and Noise Aliasing 47 -- 9.1 Impulse Train Spectrum, 47 -- 9.2 Sampling Phase Detector Noise, 47 -- 9.3 Spur Aliasing, 50 -- 10 Time and Phase Jitter, Heterodyning, and Multiplication 53 -- 10.1 Heterodyning and Resulting Time Jitter, 53 -- 10.2 Frequency Multiplication and Angle Modulation Index, 54 -- 10.3 Frequency Multiplication's Role in Carrier Recovery, 54 -- 11 Carrier Recovery Applications and Acquisition 57 -- 11.1 Frequency Multiplier Carrier Recovery in General, 57 -- 11.2 The Simplest Form of Costas PLL, 59 -- 11.3 Higher Level Quadrature Demodulation Costas PLL, 61 -- 11.4 False Lock in BPSK Costas PLL, 62 -- 11.5 Additional Measures for Prevention of False Locking, 65. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 11.6 False Lock Prevention Using DC Offset, 72 -- 12 Notes on Sweep Methods 73 -- 12.1 Sweep Waveform Superimposed Directly on VCO Input, 73 -- 12.2 Maximum Sweep Rate (Acceleration), 74 -- 12.3 False Lock due to High-Order Filtering, 77 -- 12.4 Sweep Waveform Applied Directly to PLL Loop Integrator, 79 -- 12.5 Self-Sweeping PLL, 79 -- 13 Nonsweep Acquisition Methods 85 -- 13.1 Delay Line Frequency Discriminator, 85 -- 13.2 The Fully Unbalanced Quadricorrelator, 87 -- 13.3 The Fully Balanced Quadricorrelator, 88 -- 13.4 The Multipulse Balanced Quadricorrelator, 89 -- 13.5 Conclusion Regarding Pulsed Frequency Detection, 91 -- 13.6 Quadricorrelator Linearity, 92 -- 13.7 Limiter Asymmetry due to DC Offset, 97 -- 13.8 Taylor Series Demonstrates Second-Order-Caused DC Offset, 100 -- 13.9 Third-Order Intermodulation Distortion and Taylor Series, 101 -- 14 AM Rejection in Frequency Detection Schemes 105 -- 14.1 AM Rejection with Limiter and Interferer, 105 -- 14.2 AM Rejection of the Balanced Limiter/Quadricorrelator Versus the Limiter/Discriminator in the Presence of a Single Spur, 106 -- 14.3 Impairment due to Filter Response Tilt (Asymmetry), 110 -- 14.4 Bandpass Filter Geometric and Arithmetic Symmetry, 114 -- 14.5 Comments on Degree of Scrutiny, 117 -- 15 Interfacing the Frequency Discriminator to the PLL 119 -- 15.1 Continuous Connection: Pros and Cons, 119 -- 15.2 Connection to PLL via a Dead Band, 120 -- 15.3 Switched Connection, 121 -- 16 Actual Frequency Discriminator Implementations 125 -- 16.1 Quadricorrelator, Low-Frequency Implementation, 125 -- 16.2 Frequency Ratio Calculating Circuit for Wide-Bandwidth Use, 128 -- 16.3 Dividing the Frequency and Resultant Implementation, 131 -- 16.4 Marriage of Both Frequency and Phaselock Loops, 135 -- 16.5 Comments on Spurs' Numerical Influence on the VCO, 141 -- 16.6 Frequency Compression, 143 -- 17 Clock Recovery Using a PLL 145 -- 17.1 PLL Only, 145 -- 17.2 PLL with Sideband Crystal Filter(s), 152 -- 17.3 PLL with Sideband Cavity Filter, 153. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 17.4 The Hogge Phase Detector, 161 -- 17.5 Bang-Bang Phase Detectors, 162 -- 18 Frequency Synthesis Applications 165 -- 18.1 Direct Frequency Synthesis with Wadley Loop, 166 -- 18.2 Indirect Frequency Synthesis with PLLs, 173 -- 18.3 Simple Frequency Acquisition Improvement for a PLL, 175 -- 18.4 Hybrid Frequency Synthesis with DDS and PLL, 176 -- 18.5 Phase Noise Considerations, 181 -- 18.6 Pros and Cons of DDS-Augmented Synthesis, 185 -- 18.7 Multiple Loops, 185 -- 18.8 Reference Signal Considerations and Filtering, 186 -- 18.9 SNR of Various Phase Detectors, 187 -- 18.10 Phase Detector Dead Band (Dead Zone) and Remediation, 187 -- 18.11 Sideband Energy due to DC Offset Following Phase Detector, 191 -- 18.12 Brute Force PLL Frequency Acquisition via Speedup, 193 -- 18.13 Short-Term and Long-Term Settling, 193 -- 18.14 N-over-M Synthesis, 193 -- 19 Injection Pulling of Multiple VCO's as in a Serdes 195 -- 19.1 Allowable Coupling Between any Two VCOs Versus Q and BW, 195 -- 19.2 Topology Suggestion for Eliminating the Injection Pulling, 195 -- 20 Digital PLL Example 199 -- 21 Conclusion 203 -- References 205 -- Index 209. |
| 506 1# - RESTRICTIONS ON ACCESS NOTE | |
| Terms governing access | Restricted to subscribers or individual electronic text purchasers. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | How to acquire the input frequency from an unlocked stateA phase locked loop (PLL) by itself cannot become useful until it has acquired the applied signal's frequency. Often, a PLL will never reach frequency acquisition (capture) without explicit assistive circuits. Curiously, few books on PLLs treat the topic of frequency acquisition in any depth or detail. Frequency Acquisition Techniques for Phase Locked Loops offers a no-nonsense treatment that is equally useful for engineers, technicians, and managers.Since mathematical rigor for its own sake can degenerate into intellectual "rigor mortis," the author introduces readers to the basics and delivers useful information with clear language and minimal mathematics. With most of the approaches having been developed through years of experience, this completely practical guide explores methods for achieving the locked state in a variety of conditions as it examines:. Performance limitations of phase/frequency detector-based phase locked loops. The quadricorrelator method for both continuous and sampled modes. Sawtooth ramp-and-sample phase detector and how its waveform contains frequency error information that can be extracted. The benefits of a self-sweeping, self-extinguishing topology. Sweep methods using quadrature mixer-based lock detection. The use of digital implementations versus analogFrequency Acquisition Techniques for Phase Locked Loops is an important resource for RF/microwave engineers, in particular, circuit designers; practicing electronics engineers involved in frequency synthesis, phase locked loops, carrier or clock recovery loops, radio-frequency integrated circuit design, and aerospace electronics; and managers wanting to understand the technology of phase locked loops and frequency acquisition assistance techniques or jitter attenuating loops. |
| 530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE | |
| Additional physical form available note | Also available in print. |
| 538 ## - SYSTEM DETAILS NOTE | |
| System details note | Mode of access: World Wide Web |
| 588 ## - SOURCE OF DESCRIPTION NOTE | |
| Source of description note | Description based on PDF viewed 12/22/2015. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Phase-locked loops. |
| 655 #0 - INDEX TERM--GENRE/FORM | |
| Genre/form data or focus term | Electronic books. |
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| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | IEEE Xplore (Online Service), |
| Relator term | distributor. |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | John Wiley & Sons, |
| Relator term | publisher. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Print version: |
| International Standard Book Number | 9781118168103 |
| 856 42 - ELECTRONIC LOCATION AND ACCESS | |
| Materials specified | Abstract with links to resource |
| Uniform Resource Identifier | https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6331041 |
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