CMOS sigma-delta converters : (Record no. 42460)
[ view plain ]
| 000 -LEADER | |
|---|---|
| fixed length control field | 08369nam a2200841 i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 6497231 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | IEEE |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20191218152124.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS | |
| fixed length control field | m o d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr |n||||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 151222s2013 nju ob 001 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781118569238 |
| Qualifying information | ebook |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 9781119979258 |
| Qualifying information | |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 9781118569221 |
| Qualifying information | electronic |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 1118569229 |
| Qualifying information | electronic |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 1118569237 |
| Qualifying information | electronic |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1002/9781118569238 |
| Source of number or code | doi |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (CaBNVSL)mat06497231 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (IDAMS)0b00006481d2fb08 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | CaBNVSL |
| Language of cataloging | eng |
| Description conventions | rda |
| Transcribing agency | CaBNVSL |
| Modifying agency | CaBNVSL |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK7871.99.M44 |
| Item number | R668 2013eb |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3815/9 |
| Edition number | 23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Rosa, Jos�ae M. de la, |
| Relator term | author. |
| 245 10 - TITLE STATEMENT | |
| Title | CMOS sigma-delta converters : |
| Remainder of title | practical design guide / |
| Statement of responsibility, etc. | Jos�ae M. de la Rosa and Roc�aio del R�aio. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | Hoboken [New Jersey] : |
| Name of producer, publisher, distributor, manufacturer | Wiley-Blackwell, |
| Date of production, publication, distribution, manufacture, or copyright notice | 2013. |
| 264 #2 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | [Piscataqay, New Jersey] : |
| Name of producer, publisher, distributor, manufacturer | IEEE Xplore, |
| Date of production, publication, distribution, manufacture, or copyright notice | [2013] |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1 PDF (432 pages). |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | electronic |
| Source | isbdmedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Source | rdacarrier |
| 490 1# - SERIES STATEMENT | |
| Series statement | Wiley - IEEE |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE | |
| Bibliography, etc. note | Includes bibliographical references. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | List of Abbreviations xvii -- Preface xxi -- Acknowledgements xxvii -- 1 Introduction to (SVE(B Modulators: Basic Concepts and Fundamentals 1 -- 1.1 Basics of A/D Conversion 2 -- 1.2 Basics of Sigma-Delta Modulators 8 -- 1.3 Classification of (SVE(B Modulators 15 -- 1.4 Single-Loop (SVE(B Modulators 16 -- 1.5 Cascade (SVE(B Modulators 24 -- 1.6 Multibit (SVE(B Modulators 29 -- 1.7 Band-Pass (SVE(B Modulators 36 -- 1.8 Continuous-Time (SVE(B Modulators 41 -- 1.9 Summary 49 -- 2 Circuits and Errors: Systematic Analysis and Practical Design Issues 54 -- 2.1 Nonidealities in Switched-Capacitor (SVE(B Modulators 55 -- 2.2 Finite Amplifier Gain in SC-(SVE(BMs 56 -- 2.3 Capacitor Mismatch in SC-(SVE(BMs 60 -- 2.4 Integrator Settling Error in SC-(SVE(BMs 62 -- 2.5 Circuit Noise in SC-(SVE(BMs 71 -- 2.6 Clock Jitter in SC-(SVE(BMs 75 -- 2.7 Sources of Distortion in SC-(SVE(BMs 76 -- 2.8 Nonidealities in Continuous-Time (SVE(B Modulators 80 -- 2.9 Clock Jitter in CT-(SVE(BMs 81 -- 2.10 Excess Loop Delay in CT-(SVE(BMs 85 -- 2.11 Quantizer Metastability in CT-(SVE(BMs 88 -- 2.12 Finite Amplifier Gain in CT-(SVE(BMs 89 -- 2.13 Time-Constant Error in CT-(SVE(BMs 92 -- 2.14 Finite Integrator Dynamics in CT-(SVE(BMs 94 -- 2.15 Circuit Noise in CT-(SVE(BMs 95 -- 2.16 Sources of Distortion in CT-(SVE(BMs 97 -- 2.17 Case Study: High-Level Sizing of a (SVE(BM 99 -- 2.18 Summary 107 -- 3 Behavioral Modeling and High-Level Simulation 110 -- 3.1 Systematic Design Methodology of (SVE(B Modulators 110 -- 3.2 Simulation Approaches for the High-Level Evaluation of (SVE(BMs 113 -- 3.3 Implementing (SVE(BM Behavioral Models 118 -- 3.4 Efficient Behavioral Modeling of (SVE(BM Building Blocks using C-MEX S-Functions 134 -- 3.5 SIMSIDES: A SIMULINK-Based Behavioral Simulator for (SVE(BMs 159 -- 3.6 Using SIMSIDES for the High-Level Sizing and Verification of (SVE(BMs 167 -- 3.7 Summary 183 -- 4 Circuit-Level Design, Implementation, and Verification 186 -- 4.1 Macromodeling (SVE(BMs 186 -- 4.2 Including Noise in Transient Electrical Simulations of (SVE(BMs 199 -- 4.3 Processing (SVE(BM Output Results of Electrical Simulations 208. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 4.4 Design Considerations and Simulation Test Benches of (SVE(BM Basic Building Blocks 213 -- 4.5 Auxiliary (SVE(BM Building Blocks 250 -- 4.6 Layout Design, Floorplanning, and Practical Issues 257 -- 4.7 Chip Package, Test PCB, and Experimental Set-Up 263 -- 4.8 Summary 270 -- 5 Frontiers of (SVE(B Modulators: Trends and Challenges 273 -- 5.1 Overview of the State of the Art on (SVE(BMs 274 -- 5.2 Empirical and Statistical Analysis of State-of-the-Art (SVE(BMs 291 -- 5.3 Cutting-Edge (SVE(BM Architectures and Techniques 300 -- 5.4 Classification of State-of-the-Art References 319 -- 5.5 Summary 319 -- A SIMSIDES User Guide 334 -- A.1 Getting Started: Installing and Running SIMSIDES 334 -- A.2 Building and Editing (SVE(BM Architectures in SIMSIDES 335 -- A.3 Analyzing (SVE(BMs in SIMSIDES 337 -- A.4 Example 345 -- A.5 Getting Help 354 -- B SIMSIDES Block Libraries and Models 355 -- B.1 Overview of SIMSIDES Libraries 355 -- B.2 Ideal Libraries 355 -- B.3 Real SC Building-Block Libraries 361 -- B.4 Real SI Building-Block Libraries 364 -- B.5 Real CT Building-Block Libraries 371 -- B.6 Real Quantizers and Comparators 382 -- B.7 Real D/A Converters 382 -- B.8 Auxiliary Blocks 384 -- Index 389. |
| 506 1# - RESTRICTIONS ON ACCESS NOTE | |
| Terms governing access | Restricted to subscribers or individual electronic text purchasers. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | This book offers a timely practical design guide and comprehensive description of Sigma-Delta Modulators ((SV∆(BMs). With emphasis on the most important design issues and the multiple trade-offs involved in the whole design flow from specifications to chip implementation and characterization, it compiles the enormous number of technical and research works reported to date on the topic of (SV∆(BMs, and presents the results of such a compilation in a didactical, pedagogical, and intuitive style. Various design methodologies and practical considerations are described with a top-down approach, presenting from theoretical fundamentals, system-level design equations and behavioral models in MATLAB/SIMULINK, to circuit, transistor-level realization in Cadence Design FrameWork II, and physical implementation, chip prototyping and experimental characterization.Other key features: . a comprehensive and systematic description of (SV∆(BM architectures from the basic operating principles to state-of-the-art advances in architectures and circuits, and considering both switched-capacitor and continuous-time circuit implementations. a detailed review of state-of-the-art (SV∆(BM ICs, extracting statistical and empirical design guidelines, identifying trends, design challenges and solutions. case studies showing the different stages of the design flow of (SV∆(BMs. a complete description of SIMSIDES (SIMulink Sigma-Delta Simulator), a time-domain behavioral simulator for the high-level sizing and verification of (SV∆(BMs, implemented in MATLAB/SIMULINK. a number of electronic resources (available through a companion website) including practical examples using SIMSIDES, the statistical data used in the state-of-the-art survey, as well as many design examples and simulation test benchesUsing a pedagogical and intuitive approach, this is an essential guide for designers of mixed-signal circuits in nanometer CMOS. It doubly serves as a self-contained reference for researchers, designers and non-experienced engineers wanting to acquire an insight into (SV∆(BMs and for undergraduate and graduate students in electronics engineering. |
| 530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE | |
| Additional physical form available note | Also available in print. |
| 538 ## - SYSTEM DETAILS NOTE | |
| System details note | Mode of access: World Wide Web |
| 588 ## - SOURCE OF DESCRIPTION NOTE | |
| Source of description note | Description based on PDF viewed 12/22/2015. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Metal oxide semiconductors, Complementary |
| General subdivision | Design and construction. |
| 655 #0 - INDEX TERM--GENRE/FORM | |
| Genre/form data or focus term | Electronic books. |
| 695 ## - | |
| -- | CMOS integrated circuits |
| 695 ## - | |
| -- | Capacitance |
| 695 ## - | |
| -- | Capacitors |
| 695 ## - | |
| -- | Clocks |
| 695 ## - | |
| -- | Computational modeling |
| 695 ## - | |
| -- | Computer architecture |
| 695 ## - | |
| -- | Conferences |
| 695 ## - | |
| -- | Equivalent circuits |
| 695 ## - | |
| -- | Gain |
| 695 ## - | |
| -- | Integrated circuit modeling |
| 695 ## - | |
| -- | Market research |
| 695 ## - | |
| -- | Mathematical model |
| 695 ## - | |
| -- | Modulation |
| 695 ## - | |
| -- | Nickel |
| 695 ## - | |
| -- | Noise |
| 695 ## - | |
| -- | Quantization (signal) |
| 695 ## - | |
| -- | Sections |
| 695 ## - | |
| -- | Semiconductor device modeling |
| 695 ## - | |
| -- | Sigma-delta modulation |
| 695 ## - | |
| -- | Solid state circuits |
| 695 ## - | |
| -- | Switches |
| 695 ## - | |
| -- | Topology |
| 695 ## - | |
| -- | Transfer functions |
| 695 ## - | |
| -- | Additive white noise |
| 695 ## - | |
| -- | Approximation methods |
| 695 ## - | |
| -- | Bandwidth |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | IEEE Xplore (Online Service), |
| Relator term | distributor. |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | John Wiley & Sons, |
| Relator term | publisher. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Print version: |
| International Standard Book Number | 9781119979258 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| Uniform title | Wiley - IEEE |
| 856 42 - ELECTRONIC LOCATION AND ACCESS | |
| Materials specified | Abstract with links to resource |
| Uniform Resource Identifier | https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6497231 |
No items available.