| 000 | 07868nam a2201597 i 4500 | ||
|---|---|---|---|
| 001 | 5266000 | ||
| 003 | IEEE | ||
| 005 | 20191218152117.0 | ||
| 006 | m o d | ||
| 007 | cr |n||||||||| | ||
| 008 | 100317t20152001nyua ob 001 0 eng d | ||
| 020 |
_a9780470544365 _qelectronic |
||
| 020 |
_z9780780360013 _qprint |
||
| 020 |
_z0470544368 _qelectronic |
||
| 024 | 7 |
_a10.1109/9780470544365 _2doi |
|
| 035 | _a(CaBNVSL)mat05266000 | ||
| 035 | _a(IDAMS)0b000064810c5bdf | ||
| 040 |
_aCaBNVSL _beng _erda _cCaBNVSL _dCaBNVSL |
||
| 050 | 4 |
_aTK7895.M5 _bD47 2001eb |
|
| 082 | 0 | 4 |
_a621.3815 _222 |
| 245 | 0 | 0 |
_aDesign of high-performance microprocessor circuits / _cAnantha Chandrakasan, William J. Bowhill, Frank Fox, [editors]. |
| 264 | 1 |
_aNew York : _bIEEE Press, _cc2001. |
|
| 264 | 2 |
_a[Piscataqay, New Jersey] : _bIEEE Xplore, _c[2000] |
|
| 300 |
_a1 PDF (xx, 557 pages) : _billustrations. |
||
| 336 |
_atext _2rdacontent |
||
| 337 |
_aelectronic _2isbdmedia |
||
| 338 |
_aonline resource _2rdacarrier |
||
| 504 | _aIncludes bibliographical references and index. | ||
| 505 | 0 | _aPreface. OVERVIEW. Impact of Physical Technology on Architecture (John H. Edmondson). TECHNOLOGY ISSUES. CMOS Scaling and Issues in SUB-0.25?m Systems (Yuan Taur). Techniques for Leakage Power Reduction (Vivek De, Yibin Ye, et al.). Low-Voltage Technologies (Tadahiro Kuroda and Takayasu Sakurai). SOI Technology and Circuits (Ghavam G. Shahidi, Fari Assaderaghi and Dimitri Antoniadis). Models of Process Variations in Device and Interconnect (Duane Boning and Sani Nassif). CIRCUIT STYLES FOR LOGIC. Basic Logic Families (Kerry Bernstein). Issues in Dynamic Logic Design (Paul Gronowski). Self-Timed Pipelines (Ted Williams). High-Speed VLSI Arithmetic Units: Adders and Multipliers (Vojin G. Oklobdzija). CLOCKING. Clocked Storage Elements (Hamid Partovi). Design of High-Speed CMOS PLLs and DLLs (John George Maneatis). Clock Distribution (Daniel W. Bailey). MEMORY SYSTEM DESIGN. Register Files and Caches (Ronald Preston). Embedded DRAM (Tadaaki Yamauchi and Michihiro Yamada). INTERCONNECT AND I/O. Analyzing On-Chip Interconnect Effects (Noel Menezes and Lawrence Pileggi). Techniques for Driving Interconnect (Shannon V. Morton). I/O and ESD Circuit Design (Stephen C. Thierauf and Warren R. Anderson). High-Speed Electrical Signaling (Stefanos Sidropoulos, Chih-Kong Ken Yang, and Mark Horowitz). RELIABILITY. Electromigration Reliability (J. Joseph Clement). Hot Carrier Reliability (Kaizad Mistry). CAD TOOLS AND TEST. Overview of Computer-Aided Design Tools (Yao-Tsung Yen). Timing Verification (Victor Peng). Design and Analysis of Power Distribution Networks (David Blaauw, Rajendran Panda, and Rajat Chaudhry). Testing of High-Performance Processors (Dilip K. Bhavsar). Index. | |
| 506 | 1 | _aRestricted to subscribers or individual electronic text purchasers. | |
| 520 | _aThis book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola. Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth:. Architectural constraints of CMOS VLSI design. Technology scaling, low-power devices, SOI, and process variations. Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units. Latches, clocks and clock distribution, phase-locked and delay-locked loops. Register file, cache memory, and embedded DRAM design. High-speed signaling techniques and I/O design. ESD, electromigration, and hot-carrier reliability. CAD tools, including timing verification and the analysis of power distribution schemes. Test and testability Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses. | ||
| 530 | _aAlso available in print. | ||
| 538 | _aMode of access: World Wide Web | ||
| 588 | _aDescription based on PDF viewed 12/21/2015. | ||
| 650 | 0 |
_aMicroprocessors _xDesign and construction. |
|
| 650 | 0 | _aLogic circuits. | |
| 655 | 0 | _aElectronic books. | |
| 695 | _aAdders | ||
| 695 | _aAlgorithm design and analysis | ||
| 695 | _aAluminum | ||
| 695 | _aArrays | ||
| 695 | _aCMOS integrated circuits | ||
| 695 | _aCMOS technology | ||
| 695 | _aCapacitance | ||
| 695 | _aCapacitors | ||
| 695 | _aCharge pumps | ||
| 695 | _aCircuit faults | ||
| 695 | _aCircuit synthesis | ||
| 695 | _aClamps | ||
| 695 | _aClocks | ||
| 695 | _aComputer architecture | ||
| 695 | _aConductors | ||
| 695 | _aCopper | ||
| 695 | _aCouplings | ||
| 695 | _aDecoding | ||
| 695 | _aDelay | ||
| 695 | _aDetectors | ||
| 695 | _aDielectrics | ||
| 695 | _aDoping | ||
| 695 | _aDriver circuits | ||
| 695 | _aElectric fields | ||
| 695 | _aElectromigration | ||
| 695 | _aElectron traps | ||
| 695 | _aFilms | ||
| 695 | _aFlip-flops | ||
| 695 | _aHeating | ||
| 695 | _aHot carriers | ||
| 695 | _aImage edge detection | ||
| 695 | _aImmune system | ||
| 695 | _aImpact ionization | ||
| 695 | _aImpedance | ||
| 695 | _aIndexes | ||
| 695 | _aInductance | ||
| 695 | _aInsulators | ||
| 695 | _aIntegrated circuit interconnections | ||
| 695 | _aIntegrated circuit modeling | ||
| 695 | _aInverters | ||
| 695 | _aJitter | ||
| 695 | _aLatches | ||
| 695 | _aLayout | ||
| 695 | _aLeakage current | ||
| 695 | _aLogic arrays | ||
| 695 | _aLogic gates | ||
| 695 | _aMOS devices | ||
| 695 | _aMOSFET circuits | ||
| 695 | _aMaterials | ||
| 695 | _aMetals | ||
| 695 | _aMicroprocessors | ||
| 695 | _aMultiplexing | ||
| 695 | _aNoise | ||
| 695 | _aP-n junctions | ||
| 695 | _aPhase locked loops | ||
| 695 | _aPipelines | ||
| 695 | _aPower dissipation | ||
| 695 | _aPower grids | ||
| 695 | _aPower supplies | ||
| 695 | _aPower transmission lines | ||
| 695 | _aProgram processors | ||
| 695 | _aRLC circuits | ||
| 695 | _aRails | ||
| 695 | _aRandom access memory | ||
| 695 | _aReceivers | ||
| 695 | _aReduced instruction set computing | ||
| 695 | _aReflection | ||
| 695 | _aRegisters | ||
| 695 | _aReliability | ||
| 695 | _aResistance | ||
| 695 | _aSemiconductor device modeling | ||
| 695 | _aSensors | ||
| 695 | _aSilicon | ||
| 695 | _aSolid modeling | ||
| 695 | _aSubstrates | ||
| 695 | _aSubthreshold current | ||
| 695 | _aSwitches | ||
| 695 | _aSynchronization | ||
| 695 | _aSystem-on-a-chip | ||
| 695 | _aSystematics | ||
| 695 | _aTesting | ||
| 695 | _aThreshold voltage | ||
| 695 | _aThumb | ||
| 695 | _aTiming | ||
| 695 | _aTransistors | ||
| 695 | _aTransmitters | ||
| 695 | _aTunneling | ||
| 695 | _aUncertainty | ||
| 695 | _aVery large scale integration | ||
| 695 | _aVoltage control | ||
| 695 | _aWire | ||
| 700 | 1 | _aChandrakasan, Anantha P. | |
| 700 | 1 |
_aFox, Frank, _d1952- |
|
| 700 | 1 | _aBowhill, William J. | |
| 710 | 2 |
_aJohn Wiley & Sons, _epublisher. |
|
| 710 | 2 |
_aIEEE Xplore (Online service), _edistributor. |
|
| 776 | 0 | 8 |
_iPrint version: _z9780780360013 |
| 856 | 4 | 2 |
_3Abstract with links to resource _uhttps://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5266000 |
| 999 |
_c42114 _d42114 |
||